1. Field of the Invention
The present invention relates to the structures of semiconductor transistors and to fabrication processes therefor, particularly to those of bipolar transistors.
This application is based on Patent Application No. Hei 8-278321, filed in Japan, the contents of which are incorporated herein by reference.
2. Related Art
As is well known, reduction of transistor size in bipolar transistors is very effective for reducing parasitic capacitance from the standpoint of improving microwave performance thereof.
For reducing parasitic capacitance, it is very important to isolate transistors from one another.
Generally, in the case of fabrication of Si bipolar transistors on a Si substrate, local oxidation of Si(LOCOS) processes are used for isolation. However, this is not satisfactory due to problems related to the reduction of effective transistor areas and that of the open leads caused by the birds beak.
Here, another method for isolation, a trenched-groove isolation method, in which first, grooves such as trenched-grooves are formed, and then embedded using a dielectric material, is effective, since there is no problem due to the birds beak, unlike in the LOCOS process. Therefore, the trenched-groove isolation method is preferable to reduce the minimum transistor size due to the narrower isolation area and due to the possibility of building the isolation area near an active area of the transistor.
In particular, a method using dielectric materials such as BPSG (Boro-Phospho-Silicate-Glass), etc., which can exhibit "re-flow" characteristics at high temperatures, is effective for isolating transistors with reduced parasitic capacitances. In this description, the "re-flow" characteristics means to exhibits a flowability with changing the surrounding condition, that is increasing temperature, for example.
FIGS. 21 and 16 show a first related art, which are a schematic cross section and a plan view of a conventional bipolar transistor, respectively. The schematic cross section is the view from the line XXI--XXI in FIG. 16.
As shown in these figures, a bipolar transistor A is formed on the semiconductor substrate 1, within the transistor area B in the form of an island.
In this transistor area B, a highly-doped n-type semiconductor layer 2 (collector contact layer), lightly-doped n-type semiconductor layer 3 (collector layer), p-type semiconductor layer 12 (intrinsic base layer), and the upper surface, a highly-doped n-type semiconductor layer 15 (emitter layer) is formed; consequently, an npn-type bipolar transistor structure is produced. On the outside of the npn-type bipolar transistor structure, there exists a trenched-isolator 4, which electrically isolate between the transistors and other electrical elements from one another.
In addition, the field area is covered with oxide layer 5. On the upper oxide layer of the collector leading section 19, the base leading section 18, and the opening (contact hole) of the emitter leading section, there are through holes, each for respectively contacting these electrodes and the upper lead line. Here, the base electrode 9 is formed using a highly-doped p-type poly-silicon (poly-Si), whereas the emitter electrode 16 is formed using a highly-doped n-type poly-Si. As shown in this figure, a silicon-nitride layer 10 and a side wall structure formed using a dielectric layer 14 are inserted therebetween for isolation. In addition, the base electrode 9 is in contacted with the base layer at each end section of the base layer. On each end section, the doping concentration and the depth of the base layer is greater and thicker than that of the intrinsic base region. This highly-doped and thicker region is the so-called "graft-base layer" 13.
FIGS. 17 to 21 explain the fabrication process of the bipolar transistors. First, hidghly-doped n-type semiconductor layer 2, and lightly-doped n-type layer 3 were formed on a semiconductor substrate 1. Then, the trenched-groove isolation regions 4 were formed in the outer peripheral region which surround the transistor region. Next, oxide layer 5 is formed over the entire surface of the semiconductor substrate 1, then a base contact region 7 is formed by wet etching of the upper oxide layer at the opening region of the base contact region 7, by using a photoresist as a mask 6. The remaining oxide layer 5 is then etched using anisotropic dry etching, resulting in a complete opening through the base contact region 7.
After removing the photoresist mask 6, p-type poly-Si layer 9, by addition of a p-type impurity, is deposited on the entire substrate. The base electrode was formed by etching the poly-Si layer to a predetermined shape.
Next, a nitride layer 10 was deposited on the whole surface of the substrate 1 (FIG. 19). An opening for an emitter contact is then formed by using an anisotropic dry etching of both the nitride layer 10 and a highly-doped p-type poly-Si layer. The p-type intrinsic base layer 12 and a side-wall 14 formed by dielectric materials are then formed, resulting in isolation of the highly-doped poly-Si 9 from the base electrode. A highly-doped graft-base layer 13 is formed by diffusion of the p-type impurity in the highly-doped poly-Si 9 into the semiconductor layer by heat-treatment after deposition of the highly-(doped poly-Si 9.
Finally, an emitter electrode is formed using a highly-doped poly-Si 16 doped with an n-type impurity; a highly-doped n-type emitter layer 16 is then formed by diffusing an n-type impurity into the semiconductor layer originated form the highly-doped n-type poly-Si 16 during this heat treatment.
A second related art disclosed a structure with a minimized alignment margin region using a self-aligning process. This second process forms the contact region of the base electrode using a self-aligning technique. The fabrication process is as follows.
FIG. 27 and FIG. 22 show a cross section and a plan view of the self-aligned base electrode. In this structure, as the contact region of the base-electrode is determined at the emitter opening region in a self-aligned manner, no shift in alignment during the alignment process of opening the base contact is expected, so there will be no offset of the contact region of the base electrode, resulting in constant contact of the base electrode connected to the base contact region.
The fabrication process for the above self-aligned bipolar transistors will be explained with reference to FIGS. 23 to 27. In this self-aligned transistor, as in the conventional fabrication process as explained in the first related art, after completing the opening through the base contact region 7 and removing the photoresist mask, the base contact region is covered by about a 50-nm-thick spacer oxide Layer 8 grown using a thermal oxidation method. Next, p-type poly-Si is grown over the entire surface, followed by the processes to form a desired shape and covering the whole surface with nitride 10.
The opening of the emitter region is then formed using anisotropic dry etching of a nitride layer 10 and a highly-doped p-type poly-Si layer, and next, partial wet etching is performed to etch the spacer oxide layer 8 near the openings. After this, the substrate is covered with poly-Si which was embedded under the highly-doped poly-Si 9, under which the spacer oxide layer 8 was side-etched by previous wet etching.
Poly-Si layer 11 is then etched back using an isotropic dry etching; poly-Si can remain only under the highly-doped poly-Si layer 9 where the spacer oxide layer 8 was side-etched. Then, the p-type intrinsic base layer 12 is formed, and then dielectric side-wall 14 was formed in order to isolate the emitter electrode of the highly-doped p-type poly-Si 9 and a base electrode. A highly-doped grafted-base layer 13 is formed by heat treatment after connecting it to the semiconductor area via poly-Si 11. The heat treatment enhances the diffusion of the p-type impurity originally doped in the highly-doped poly-Si layer 9, into the semiconductor area via poly-Si 11.
Finally, an emitter electrode is formed using a highly-doped n-type poly-Si 16. The highly-doped n-type emitter layer 15 is formed by diffusion of the n-type impurity originating from the poly-Si 16 into the semiconductor layer by heat treatment.
Therefore, fabricated bipolar transistors can determine the width of the contact area of the base electrode with respect to the emitter opening region by using a self-aligning technique; there will be no shift of alignment when opening the base contact, and there will be no offset of the contact region of the base electrode, resulting in good contact of the base electrode.
Japanese Patent Application, First Publication, No. Sho 63-72159 discloses the third related art, which will be explained using FIGS. 28 and 29 thereof. In this structure, bipolar transistors are isolated using a trenched-groove 4, and the emitter area 8 and the base contact region 7 was self-aligned with respect to the isolation trench 4. As a result, the alignment margin can be reduced, resulting in a reduction of device size, which has a merit of easy fabrication for high-density integrated circuits.
However, in the above three related arts, there are some problems to be solved.
In the first related art, the photoresist mask 6 for the opening of the base contact 7 should be formed to the inside of the base contact 7 by about 0.3 micron, because the base contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of the isolation trench 4 in the conventional alignment process.
In addition, when forming the opening of the emitter region, the emitter region should be formed to the inside of the base contact 7 by about 0.5 microns because the base contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of the isolation trench 4 in the conventional alignment process to ensure that the base electrode contact width is larger than 0.2 microns, even if there exists a shift of the base contact region 17 in the same direction of the above shift in alignment.
These problems presented a more difficult hurdle in reducing the transistor size, as the alignment margin area took up a larger proportion relative to the whole transistor area, thereby hindering further progress in device miniaturization.
In the second related art, the problem is that the alignment margin of the opening for the base contact 7 with respect to the edge of an isolation trench is not much improved. Only a 0.2 micron improvement is achieved over the above first related art because of lack of improvement in the alignment margin of the opening with respect to the edge of the isolation trench 4.
Furthermore, in the third related art, the problem remains of the formation of a large parasitic capacitance of poly-Si in the region around the collector region formed by the highly-doped n-type semiconductor layer 2 and the lightly-doped n-type semiconductor layer 3, because the highly-doped p-type poly-Si base electrode 9 was connected to the poly-Si in the trenched-groove, which will hinder an improvement in the microwave performance of transistors. As the poly-Si buried in the trenched-groove 4 itself does not exhibit conductivity, it does not function as a base electrode up to the bottom of the trenched-groove 4.
However, as the impurities in the highly-doped p-type poly-Si base electrode 9 can easily diffuse into the poly-Si in the trenched-groove 4, the region functioning as a base electrode is unnecessarily spread over a large area, resulting in increased capacitances between the base and the collector, as well as between the base and the substrate. Moreover, in the bottom portion of the trenched-groove 4, which does not function as abase electrode, the poly-Si functions as a capacitor between the collector and the substrate, introducing the problem of formation of large capacitance due to the high dielectric constant of poly-Si compared to the dielectric layer.